VIA Apollo Pro 133A & VCSDRAM - Part 1: The Technology

Below you'll find a diagram of how a single memory master accesses data from system memory:

This is where Virtual Channel architecture comes into play. Virtual Channel Memory uses a set of high speed static registers (high speed memory) between the memory core and I/O pins (between the memory itself and its connection to the "outside world" or memory masters). These high speed registers provide each memory master with its own "Virtual Channel" to the SDRAM. This helps reduce latency and increase the efficiency of the amount of bandwidth available to your system as a whole.

Specifically, VC-SDRAM features 16 virtual channels, each 128 bytes in width. The 16 channels are split evenly among the two internal banks each VC-SDRAM module features.

Unlike DDR-SDRAM, VC-SDRAM does not increase memory bandwidth by a fixed amount but it frees up bandwidth for use as a result of greater memory bus efficiency. NEC claims a figure of up to 90% efficiency, but that depends entirely on the number of memory masters accessing memory and the nature of each access.

At the same time, VC-SDRAM does not decrease latency by a fixed amount; rather, it depends on the nature of the accesses it decreases the latency for simultaneous accesses by multiple memory masters.